The present application relates to semiconductor technology, and more particularly to a method of forming a semiconductor structure comprising a III-V compound semiconductor fin that has a bottommost surface located directly on a surface of a dielectric material that is provided atop a surface of a bulk semiconductor substrate.
For more than three decades, the continued miniaturization of metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various showstoppers to continued scaling have been predicated for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that metal oxide semiconductor transistors are beginning to reach their traditional scaling limits. Since it has become increasingly difficult to improve MOSFETs and therefore complementary metal oxide semiconductor (CMOS) performance through continued scaling, further methods for improving performance in addition to scaling have become critical.
The use of non-planar semiconductor devices such as, for example, semiconductor fin field effect transistors (FinFETs), is the next step in the evolution of complementary metal oxide semiconductor (CMOS) devices. Semiconductor fin field effect transistors (FinFETs) can achieve higher drive currents with increasingly smaller dimensions as compared to conventional planar FETs. In order to extend these devices for multiple technology nodes, there is a need to boost the performance with high mobility semiconductor channel materials such as, for example, III-V compound semiconductor materials. Moreover, semiconductor fins containing a III-V compound semiconductor that are formed on an insulator material would be beneficial for better short channel effects.